1. Field of the Invention
The present invention relates to multiplication of a clock frequency, and more particularly to a clock multiplier capable of efficiently operating in a low frequency region and a clock generator including the clock multiplier.
2. Description of the Related Art
Generally, a clock multiplier in an integrated circuit generates internal clocks used for the inner circuits of the integrated circuit by multiplying the frequency of an input clock signal. Thus, although an input clock having a relatively low frequency is inputted to the integrated circuit, the clock multiplier can generate a clock having a relatively high frequency desirable to the integrated circuit.
A conventional clock multiplier typically includes a phase locked loop (PLL) or a delay locked loop (DLL).
Generally, a clock multiplier using the PLL detects a phase/frequency difference between division clocks (FIN/N, FOUT/N) corresponding to clocks divided frequencies of an input clock (FIN) and an output clock (FOUT) by N, and the clock multiplier using the PLL controls the frequency of the output clock (FOUT) based on the result of the detection.
However, the clock multiplier using the PLL requires a specific time for controlling the phase/frequency difference of the input clock and the output clock, and an error of the clock multiplier may be accumulated until the error is compensated with respect to the next input clock. When the frequency of an input clock of the clock multiplier using the PLL is about several tens of KHz, an error of the clock multiplier may accumulate more.
Generally, a clock multiplier using the DLL detects a phase/frequency difference between an input clock (FIN) and an output clock (FOUT), and controls the delay of a plurality of delay cells included in a delay line based on the result of the detection.
However, when a multiplication ratio is increased, a problem may occur such that the phase/frequency difference is increased among delay signals outputted from the delay cells. When the multiplication ratio is decreased, the phase/frequency difference is decreased among delay signals outputted from the delay cells. Thus, the clock multiplier using the DLL also does not efficiently operate in the low frequency region.
For example, when a clock multiplier receives an input clock having a period of 8 μs and generates an output clock having a period of 1 μs, the clock multiplier is required to include 16 delay cells each having a delay time of 8/16 μs. However, it is difficult to obtain a delay time of 0.5 μs with a conventional current starved delay cell. In current starved delay cells, a p-bias (gate bias to a PMOS device) is generated by a current mirror (a PMOS transistor connected as a MOS diode). A current-starved delay cell has two inverter stages, a voltage-controlled positive-channel metal oxide semiconductor (PMOS) current source and a voltage-controlled negative-channel metal oxide semiconductor (NMOS) current source (see FIG. 2). The two sources control the delay period of the delay cell.